Delivering superior throughput for EDA verification workloads

Published by: Gord Sissons

During September of 2018, members of our Cabot Partners team had the opportunity to work with talented engineers and industry experts from HPE, Cadence, Marvell, and Arm. We collaborated to develop a whitepaper and conduct preliminary benchmarks showing how new Cadence tools optimized for multi-core systems benefit from Marvell ThunderX2 Arm-based systems such as the HPE Apollo 70 system.

Arm datacenter systems are fast becoming a force to be reckoned with in HPC. You can read our published HPE whitepaper here.

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging system-on-a-chip (SoC) designs for an increasingly connected world. With the number of IoT devices forecast to grow to over 75 billion by 2025, consumers and manufacturers are all about durability, safety, battery life, and security including resistance to malware and hacking attempts.

This level of change is unprecedented. Chip designers are faced with seemingly irreconcilable pressures such as shorter product design cycles, increasing complexity, increased requirements for quality, and continuous pressures on costs.

In this paper, we discuss the challenge of device verification, a key issue in EDA, and explain how new high-performance systems and software are promising to improve the economics of chip design enabling firms to innovate faster and create high-quality products.



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